1. Field of the Invention
The present invention relates to a method and an apparatus for interpolating image signals, and more particularly, it relates to a method and an apparatus for interpolating image signals in processing of input and output images which are different in number of pixels.
2. Description of the Prior Art
In order to, for example, enlarge or reduce images, it is necessary to output the images in a different number of pixels from that of input images. Generally well known is technique of varying magnifications of images for an image processing device such as a process scanner, a laser printer, a facsimile or the like which temporarily stores image data in a memory having storage capacity for, e.g., one scanning line while relatively varying pixel clocks (or memory addresses) for writing and reading the image data in and from the memory with target magnifications thereby to increase or decrease the number of pixels. Examples of such technique are as follows:
A first system employs a frequency divinding circuit included in a PLL circuit, the frequencey dividing ratio of whech is varied to change pixel clock frequencies in writing and reading operations as disclosed in, e.g., Japanese Patent Publication Gazette No. 50561/1977. Although such a method substantially has no problem in a low frequency range, the PLL circuit is complicated in stucture and a high-speed processing circuit (device) is required in order to obtain outputs of a highly enlarged magnification value in an apparatus requiring processing in a high frequencey range, whereby the cost is inevitably increased.
In a second system, pixel clocks are employed in such a manner that additional pulses are inserted between ordinary periodic peixel clocks, i.e., synchronous pulse trains, as disclosed in, e.g., Japanese Patent Laying-Open Gazette No. 11601/1978. Such pixel clocks are adapted to designate addresses for writing in a memory while the original pixel clocks are adapted to designate addresses for reading from the memory, whereby reproduced pixels in the pattern of an original are increased in number in comparision with the pixels read or sampled from the original to provide enlarged image outputs. On the other hand, the pixel clocks may be adapted to designate the addresses for reading, thereby to obtain reduced image outputs. In such a system, however, the additional pulses must be inserted between the pulse trains in predetermined periods, whereby designation of magnifications for varying the same is restricted to, e.g., a range of 50 to 200% in the embodiment as disclosed in the Japanese Patent Laying-Open Gazette No. 11601/1978. Further, the magnification settable intervals are restricted to (n+1)/n.times.100% (n: integer), i.e., 1/2, 2/3, . . . 1, . . . 3/2 and 2/1.
A third system writes image data in a memory at a constant frequency (pexel clock) or sampling pitch to access the same with memory addresses being partially defaulted for reduction or duplicated for enlargement, thereby to decrease or increase the number of outputted pixels, as disclosed in, e.g., Japanese Patent Laying-Open Gazettes Nos. 65601/1979 and 35613/1979. According to such technique, distribution of the defaulted or duplicated addresses is averaged to considerably reduce uneveness of outputted images in reduction or enlargement, whereas the circuit structure for such averaging is complicated. Such a tendency is spurred by increase in the range of magnifications.
In the conventional magnification varying systems, thus, it has been difficult to obtain images in which additional pixels are evenly distributed in a wide magnification range with relatively simple circuit structure.
Further, the output operation is performed only through the pixel data written in the memory in each of the aforementioned systems, and hence continuous pixels in specific gradation are unexpectedly followed by those in different gradation when identical pixel data are repeated in a reproduced image in enlargement, whereby space gradation in the reproduced image cannot be smoothly changed.
In addition to the aforementioned case of enlargement and reduction, it is also necessary to output an image in a different number of pixels from that of the input image in order to obtain, e.g., an output image in resolution higher than that of the input image as hereinafter described.
In case where one-dimensional photoelectric conversion element array device such as a CCD line sensor, a CPD line sensor or a MOS-type line sensor is applied to, e.g., a process scanner which requires high output resolution, the upper limit of input resolution depends on the form and characteristics specific to the one-dimensional photoelectric conversion element array device as employed. In other words, the one-dimensional photoelectric conversion element array device is formed by a number of linearly arrayed photoelectric conversion elements having prescribed areas so that main scanning is performed along the direction of the array, and hence the input resolution in the main scanning direction is determined by the number of the photolectric conversion elements. In order to improve the input resolution in the main scanning direction, therefore, it is necessary to increase the number of the photoelectric conversion elements included in the one-dimensional photoelectric conversion element array device, whereas such increase is restricted as for a device.
On the other hand, input resolution in the vertical scanning direction is determined by the form, the charge storage time and the vertical scanning speed of, e.g., a storage type of such a device. Therefore, the input resolution in the vertical direction can be improved without changing the form of the device by increasing the amount of incident light to reduce the storage time, whereas intense illumination is required to cause other problems such as heat generation in an illumination system. Even if the storage time can be reduced by intensifying the illumination for an original, the signal charges thus obtained and read at a high speed within the said storage time cannot be followed by the conversion speed of an A-D converter in a subsequent stage in wide gradation (e.g., 12 bits) required for process and, therefore, required is processing such as parallel processing through a plurality of costly A-D converters, leading to a complicated processing circuit with increase in cost.
Also proposed is a method of forming a process scanner of high resolution by arraying a plurality of one-dimensional photoelectric conversion element array devices in a linear or zigzag manner, whereas, in such a method, registration of the one-dimensional photoelectric conversion element array devices and adjustment of optical systems are complicated while a circuit for processing image signals thus obtained is complicated with increase in cost.
Consequently, it is not advisable to improve input resolution to a level equivalent to output resolution in the case of an apparatus such as a process scanner which requires high output resolution. In consideration of characteristics of the one-dimensional photoelectric conversion element array device such as a CCD line sensor and an A-D converter employed therein, it is rather preferable to set the input resolution to be lower than the output resolution while compensating the difference between the same by increasing the number of pixels of the input image through appropriate image processing thereby to obtain an effect substantially equivalent to that in the case of high input resolution. Also in this case, it is preferable that gradation of the output image is not abruptly changed, similarly to the aforementioned case of enlargement, to obtain an output image of smooth picture quality.